TSMC is rushing to produce 10's of millions of chips for the next iPhone, taking up nearly all their 2018 capacity at the new 7 nm node. Qualcomm and possibly Huawei have the chips at an advanced stage of design and should have sample chips in the next few months.
Rick Merritt at EE Times reports, "TSMC is in volume production of 7-nm chips today with more than 50 tapeouts expected this year. It’s making CPUs, GPUs, AI accelerators, cryptocurrency mining ASICs, networking, gaming, 5G, and automotive chips."
Rick adds, "The new normal for performance gains and power reductions generally fall in a 10% to 20% range, a reality that makes the new packaging and specialty processes increasingly important." In other words, Moore's Law ain't dead but it's slowing down. TSMC is already building the 5 nm plant and taking delivery of EUV lithography gear. Both TSMC and Samsung have committed to $20B 3 nm fabs early next decade.
The first millimeter wave chips are likely to be power-hungry and may run hot. Linley estimates it will require as much as 10X the processing power as early LTE chips. The radio frequency front end will need to work from 600 MHz to 30 GHz or more. Carriers will require many more bands, puching the state of the art. Thousands of engineers are required.
TSMC's next five years
In 2019, TSMC expects to produce 10's of millions of seven nanometer chips, maybe more. Some will be made with EUV lithography. Numerous inprovements will come. They say, "Compared to its 10nm FinFET process, TSMC's 7nm FinFET features 1.6X logic density, ~20% speed improvement, and ~40% power reduction. TSMC set another industry record by launching two separate 7nm FinFET tracks: one optimized for mobile applications, the other for high performance computing applications."
5 nm "risk production" is expected late in 2019. "MC's 5nm Fin Field-Effect Transistor (FinFET) process technology is optimized for both mobile and high performance computing applications. It is scheduled to start risk production in the second quarter of 2019. Compared to its 7nm FinFET Plus process, TSMC's 5nm FinFET adopts EUV Lithography for more critical layers to reduce multi-pattern process complexity while achieving aggressive die area scaling." Merritt expects, "Compared to the initial 7 nm without EUV, the 5-nm node promises a 1.8x greater density than 7 nm. However, it is only expected to reduce power by up to 20% or raise speeds by about 15%, perhaps 25% using Extremely Low Threshold Voltage (ELTV),"